This invention relates to an improved wafer alignment mark for alignment of a wafer and mask in a semiconductor fabrication process, and to an improved wafer fabrication process for forming wafer alignment marks.
In order to describe the invention and the problem is addresses, it will be useful to begin with a fairly detailed description of the relevant prior art.
With reference to FIG. 1, a semiconductor wafer 2 comprises a crystalline silicon substrate on which circuit and device patterns are formed by a sequence of photolithographic processes, each of which requires the wafer 2 to be exposed to light through a mask. In each photolithographic process, wafer alignment marks 4 are formed to enable precise alignment between the wafer 2 and the mask in the next photolithographic process. It is desirable that the wafer and mask be alignable by an automatic alignment system without human intervention.
An alignment mark has the configuration shown in FIG. 2, comprising a chevron 6 and two stripes 8, the stripes 8 being parallel to the two branches of the chevron 6. The width A of the chevron 6 and stripes 8 is generally from 5 to 20 micrometers, and the stripes 8 are separated from the chevron 6 by a distance B of 50 to 150 micrometers.
FIG. 3 shows a sectional view through the short dimension of an alignment-mark pattern at a point in the process when the wafer 2 is covered by a transparent photoresist 10. The wafer alignment mark pattern is formed as a depression 12 in the wafer 2. Light 14 incident on the wafer 2 is scattered at the edges 13 of the depression 12. Using standard dark-field microscopy techniques, the wafer 2 can be illuminated from an angle such that the scattered light 10 is focused onto a photodiode array (not shown in the drawing) while light reflected from flat parts of the wafer 2 is not focused onto the array.
FIG. 4A shows the signal output by the photodiode array when illuminated by scattered light from the wafer 2 in FIG. 3. The edges 18 of the depression 12 in FIG. 3 are detected as a pair of peaks 18 in the output signal the separation T.sub.1 between the peaks corresponding to the pattern width A in FIG. 2.
Light is scattered not only by the edges 13 of the depression 12 in FIG. 3 but also by dirt or projections on the surface of the wafer 2, so the output from the photodiode array may be confused by noise. For example, instead of the signal in FIG. 4A, the signal in FIG. 4B may be obtained, containing both peaks 18 representing the edges of the wafer alignment mark and extraneous peaks 20. To eliminate the extraneous peaks 20, the signal is processed by pattern recognition equipment (not shown in the drawings) that recognizes only pairs of peaks with a separation of T.sub.1. In FIG. 4B T.sub.2 &gt;T.sub.1 &gt;T.sub.3, so the pattern-recognition equipment rejects the extraneous peaks 20 and recognizes only the peaks 18, giving the same result as in FIG. 4A.
The mask which is to be aligned to the wafer is provided with mask alignment marks in positions corresponding to the wafer alignment marks. With reference to FIG. 5, a mask alignment mark comprises two pairs of parallel slits 22, each slit about two or three micrometers in width. The two slits in each pair are separated by a distance equal to the width A of the mask alignment mark, so that they can be recognized by the pattern-recognition equipment. The mask and wafer are correctly aligned when the pairs of parallel slits 22 of the mask alignment mark are disposed midway between the chevron 6 and stripes 8 of the wafer alignment mark, as shown in FIG. 5.
Alignment is performed by placing the wafer and mask in approximately the correct relative position, illuminating them, and detecting scattered light as described above. In FIG. 6A three pairs of peaks are detected, a first pair 24 representing the chevron in the wafer alignment mark, a second pair 20 representing a pair of slits in the mask alignment mark, and a third pair 28 representing a stripe in the wafer alignment mark. The distance T.sub.4 between the first and second pairs is unequal to the distance T.sub.5 between the second and third pairs, indicating that the wafer and mask are incorrectly aligned. The mask or wafer is accordingly moved under automatic control until, as shown in FIG. 6B, the distances T.sub.6 and T.sub.7 between the middle pair of peaks and the other two pairs of peaks are equal. The required motion can be calculated automatically from the distances T.sub.4 and T.sub.5 in FIG. 6A.
With reference again to FIG. 5, the alignment process is performed by scanning the alignment marks in both of the directions indicated by the arrows, thus defining a unique point of correct alignment. The alignment process is performed at two or more alignment marks disposed on different parts of the wafer, as shown in FIG. 1, thereby defining two or more correctly aligned points, ensuring that the entire wafer and mask are aligned in a unique correct relative position.
Alignment marks are formed, for example, during the part of the bipolar semiconductor fabrication process that creates n-type diffusion areas in a p-type silicon substrate. An alignment mark is created as an extra n-type diffusion area with the chevron-and-stripes shape shown in FIG. 2. The prior-art process is illustrated in FIG. 7.
In step (a) in FIG. 7, a p-type silicon substrate 20 is heated to 1040.degree. C. for three hours in a wet oxygen atmosphere to grow an oxide layer 30, which is then patterned by photolithography and etched to open windows 82 for creating the diffusion areas and alignment marks. The substrate 20 basically has a &lt;100&gt; or &lt;111&gt; crystal orientation, but it is standard practice to tilt the orientation a few degrees the occurrence of surface defects on the substrate 20, below the oxide layer 30, as described in Japanese Patent Application Publication No. 182/1975, and to reduce slumping and dislocations after epitaxial growth, as described on page 87 of the book Shirikon Kesshou to Dopingu (Silicon Crystals and Doping) published by Maruzen in Japan.
In step (b) in FIG. 7, an antimony-silica film 34 with a thickness of 2000 to 3000 angstroms is spin-coated onto the wafer as an n-type dopant source.
In step (c) in FIG. 7, the wafer is heated to 1250.degree. C. for four hours in an inert (N.sub.2) atmosphere causing the formation of an n-type buried layer 36 with a diffusion depth of five micrometers and sheet resistance of 20 ohms per square. During this step a small amount of oxygen is added to the inert atmosphere, or the wafer is oxidized in an oxygen atmosphere afterward. Since the rate of oxidation is faster over the buried layer 36 than on the part of the substrate 20 covered by the oxide layer 30, a depressed pattern is created in the substrate 29 with edges 38 and 30. The mechanism by which these edges 38 and 39 are formed is well understood: a detailed discussion will be omitted. The oxidation process is anisotropic, so the edges 38 and 39 have straight, symmetrical slopes of substantially 3.degree. to 10.degree., the exact angle depending on the temperature and oxygen conditions.
In step (d) in FIG. 7, a hydrofluoric acid etchant is used to remove the oxide layer 50 in preparation for epitaxial growth. The edges 38 and 39 remain intact.
In step (e) in FIG. 7, epitaxial growth is carried out to form an n-type epitaxial layer 40. The slopes of the edges 38 and 39 are transferred to the epitaxial layer 40, creating a depressed pattern with edges 42 and 43 on the surface of the epitaxial layer 40. Although the edges 38 and 39 are symmetrical, due to the deviation of the substrate 20 from the exact &lt;100&gt; or &lt;111&gt; crystal orientation, the edges 38 and 39 have different crystallographic structures which, for reasons not yet completely understood, cause the edges 42 and 4S on the epitaxial layer to slump to different degrees. In FIG. 7 the edge 4S does not slump and has substantially the same slope as the edge 50, but the edge 42 slumps considerably and acquires a much more gentle slope.
In step (f) in FIG. 7, an oxide layer 44 is grown as an isolation diffusion mask, then a transparent photoresist 48 is spin-coated in preparation for further photolithography. In the succeeding photolithographic process a new mask must be aligned with wafer alignment marks defined by edges such as the edges 42 and 43.
Next a common problem occurring in mask alignment after epitaxial growth will be described with reference to FIGS. 8 to 10.
With reference to FIG. 8, in the alignment process the wafer is illuminated through the photoresist 40 to detect light scattered from the edges 42 and 48 using a photodiode array, as already explained. Due to the difference in slopes, however, light 48 scattered from the edge 42 returns at a higher angle than light 40 scattered from the edge 43.
With reference to FIG. 9, because of the different scattering angles, the edge 42 produces only a low peak 50 in the output of the photodiode array, while the edge 42 produces a normal high peak 51.
With reference to FIG. 10, when it attempts to align the mask and wafer, the automatic alignment system sees a low peak 50 and high peak 51 representing one part of the wafer alignment mark, two high peaks 52 and 53 representing the mask alignment mark, and a low peak 54 and high peak 55 representing another part of the wafer alignment mark. The low peaks 50 and 54, however, are below the threshold of detection and are ignored, and since the high peaks 51 and 55 fail to be paired with peaks at the necessary separation T.sub.1, they too are ignored. Automatic alignment therefore fails and the wafer and the mask must be aligned by a human operator.
If the detection threshold is lowered in order to detect low peaks such as the peaks 50 and 54, a large amount of noise will also be detected. The automatic alignment system is then unable to discriminate between alignment-mark peaks and noise and may mis-align the mask and wafer, causing an entire defective wafer to be produced.